AO6802 30v dual n-channel mosfet general description product summary v ds i d (at v gs =10v) 3.5a r ds(on) (at v gs =10v) < 50m w r ds(on) (at v gs = 4.5v) < 70m w symbol v ds v gs i dm t j , t stg symbol t 10s steady-state steady-state r q jl 30v maximum 30 20 absolute maximum ratings t a =25c unless otherwise noted gate-source voltage units parameter t a =25c t a =70c i d 3.5 3 the AO6802 uses advanced trench technology to provide excellent r ds(on) and low gate charge. this device is suitable for use as a load switch or in p wm applications. v drain-source voltage v 20 1.15 0.73 a units 110 w c t a =25c parameter typ max -55 to 150 maximum junction-to-ambient a thermal characteristics t a =70c junction and storage temperature range power dissipation b p d pulsed drain current c continuous drain current c/w maximum junction-to-lead c/w c/w maximum junction-to-ambient a d 64 80 106 150 r q ja 78 tsop6 top view bottom view pin1 top view s2 s1 g2 g 1 d 2 d 1 1 2 3 6 5 4 g2 d2 s2 g1 d1 s1 rev 2: mar 2011 www.aosmd.com page 1 of 5
AO6802 symbol min typ max units bv dss 30 v v ds =30v, v gs =0v 1 t j =55c 5 i gss 100 na v gs(th) gate threshold voltage 1.5 2 2.5 v i d(on) 20 a 40 50 t j =125c 61 77 52 70 m w g fs 12 s v sd 0.79 1 v i s 1.5 a c iss 170 210 pf c oss 35 pf c rss 23 pf r g 1.7 3.5 5.3 w q g (10v) 4.05 5 nc q g (4.5v) 2 3 nc q gs 0.55 nc q gd 1 nc t d(on) 4.5 ns t r 1.5 ns t d(off) 18.5 ns t f 15.5 ns t rr 7.5 10 ns q rr 2.5 nc this product has been designed and qualified for th e consumer market. applications or uses as critical components in life support devices or systems are n ot authorized. aos does not assume any liability ar ising out of such applications or uses of its products. aos reserves the right to improve product design, functions and reliability without notice. m a i dss zero gate voltage drain current i d =250 m a, v gs =0v electrical characteristics (t j =25c unless otherwise noted) static parameters parameter conditions r ds(on) static drain-source on-resistance maximum body-diode continuous current input capacitance dynamic parameters v ds =v gs i d =250 m a total gate charge v gs =10v, v ds =15v, i d =3.5a gate source charge gate drain charge total gate charge output capacitance v gs =10v, v ds =5v v gs =10v, i d =3.5a body diode reverse recovery time drain-source breakdown voltage on state drain current turn-on delaytime gate-body leakage current forward transconductance diode forward voltage v ds =0v, v gs = 20v m w i s =1a,v gs =0v v ds =5v, i d =3.5a v gs =4.5v, i d =2a v gs =0v, v ds =15v, f=1mhz switching parameters gate resistance v gs =0v, v ds =0v, f=1mhz reverse transfer capacitance body diode reverse recovery charge i f =3.5a, di/dt=100a/ m s turn-off fall time turn-on rise time turn-off delaytime v gs =10v, v ds =15v, r l =4.2 w , r gen =3 w i f =3.5a, di/dt=100a/ m s a. the value of r q ja is measured with the device mounted on 1in 2 fr-4 board with 2oz. copper, in a still air enviro nment with t a =25c. the value in any given application depends on the user's spec ific board design. b. the power dissipation p d is based on t j(max) =150c, using 10s junction-to-ambient thermal resistance. c. repetitive rating, pulse width limited by junct ion temperature t j(max) =150c. ratings are based on low frequency and duty cycles to keep initialt j =25c. d. the r q ja is the sum of the thermal impedence from junction to lead r q jl and lead to ambient. e. the static characteristics in figures 1 to 6 are obtained using <300 m s pulses, duty cycle 0.5% max. f. these curves are based on the junction-to-ambien t thermal impedence which is measured with the devi ce mounted on 1in 2 fr-4 board with 2oz. copper, assuming a maximum junction temperatur e of t j(max) =150c. the soa curve provides a single pulse ratin g. rev 2: mar 2011 www.aosmd.com page 2 of 5
AO6802 n-channel: typical electrical and thermal characteristics 17 52 10 0 18 40 0 2 4 6 8 10 0.5 1 1.5 2 2.5 3 3.5 4 4.5 v gs (volts) figure 2: transfer characteristics (note e) i d (a) 30 40 50 60 70 0 2 4 6 8 10 i d (a) figure 3: on-resistance vs. drain current and gate voltage (note e) r ds(on) (m w ww w ) 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 1.0e+02 0.0 0.2 0.4 0.6 0.8 1.0 1.2 v sd (volts) figure 6: body-diode characteristics (note e) i s (a) 25c 125c 0.8 1 1.2 1.4 1.6 1.8 0 25 50 75 100 125 150 175 temperature (c) figure 4: on-resistance vs. junction temperature (note e) normalized on-resistance v gs =4.5v i d =2a v gs =10v i d =3.5a 20 40 60 80 100 120 2 4 6 8 10 v gs (volts) figure 5: on-resistance vs. gate-source voltage (note e) r ds(on) (m w ww w ) 25c 125c v ds =5v v gs =4.5v v gs =10v i d =3.5a 25c 125c 0 3 6 9 12 15 0 1 2 3 4 5 v ds (volts) fig 1: on-region characteristics (note e) i d (a) v gs =3v 3.5v 10v 4v 4.5v 7v rev 2: mar 2011 www.aosmd.com page 3 of 5
AO6802 n-channel: typical electrical and thermal characteristics 0 2 4 6 8 10 0 1 2 3 4 5 q g (nc) figure 7: gate-charge characteristics v gs (volts) 0 50 100 150 200 250 300 0 5 10 15 20 25 30 v ds (volts) figure 8: capacitance characteristics capacitance (pf) c iss c oss c rss v ds =15v i d =3.5a 1 10 100 1000 0.00001 0.001 0.1 10 1000 pulse width (s) figure 10: single pulse power rating junction-to-ambient (note f) power (w) t a =25c 0.0 0.1 1.0 10.0 100.0 0.01 0.1 1 10 100 v ds (volts) i d (amps) figure 9: maximum forward biased safe operating area (note f) 10 m s 10s 1ms dc r ds(on) limited t j(max) =150c t a =25c 100 m s 10ms 0.001 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 pulse width (s) figure 11: normalized maximum transient thermal imp edance (note f) z q qq q ja normalized transient thermal resistance in descending order d=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse d=t on /t t j,pk =t a +p dm .z q ja .r q ja r q ja =150c/w t on t p d single pulse rev 2: mar 2011 www.aosmd.com page 4 of 5
AO6802 - + vdc ig vds dut - + vdc vgs vgs 10v qg qgs qgd charge gate charge test circuit & waveform - + vdc dut vdd vgs vds vgs rl rg vgs vds 10% 90% resistive switching test circuit & waveforms t t r d(on) t on t d(off) t f t off vdd vgs id vgs rg dut - + vdc l vgs vds id vgs bv i unclamped inductive switching (uis) test circuit & waveforms ig vgs - + vdc dut l vds vgs vds isd isd diode recovery test circuit & waveforms vds - vds + i f ar dss 2 e = 1/2 li di/dt i rm rr vdd vdd q = - idt ar ar t rr rev 2: mar 2011 www.aosmd.com page 5 of 5
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